TTL NAND GATE
The transister-transister logic (TTL) is the most successful bipolar (two inputs) logic.
TTL logic gates are built only around transistors to perform logic fucntion and to provide high output device capability. A transistor is a semiconductor device uded to amplify or switch electrical signal and power.
TTL consists of two parts as follows:
1. Input - It consist of multiemitter transister and n-p-n transister.
2. output - consist of two n-p-n transister.
The NAND GATE circuit :
In the diagram multiemitter transister is represented by Q1 and each emitter acts like a diode (an electical compronent that allow the flow of current in only one direction).
Transister Q2 acts as a phase splitter, it provides simultaneous outputs from its collector and emitter.
The output transister Q3 & Q4 from a totempole connection. with a totempole connection output stage either high or low transister is ON. when Q3 is ON, the output id high and when Q4 is ON, the output is low.
The stacking of Q4, D ,Q3 and R4 is advantageous as th diode D ensures that both Q3 & Q4 transister are never switched on simultaneously.
| Input(A) | Input(B) | Output(Y ) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
CASE 1: When A =0, B =0
Input A & B is be under Forward biased and acts as closed switch allow to follow current towards Ground. Emitter Q1 is logic low connected to base of Q2. Therefore emitter of Q2 is off. This force Q3 ON and Q4 into off condition. The output Y is High.
CASE 2: When A=0, B=1
Input A is be under Forward biased and acts as closed switch allow to follow current towards Ground. Input B under Reverse biased and acts as open switch does’t allow to follow current towards ground.It causing Q2 off,Q3 ON. Therefore Q4 is off. The output Y is High.
CASE 3: A=1, B=0
Input B is be under Forward biased and acts as closed switch allow to follow current towards Ground. Input A under Reverse biased and acts as open switch doesn’t allow to follow current towards ground.It causing Q2 off,Q3 ON. Therefore Q4 is off. The output Y is High.
CASE 4: A=1, B=1
Input A & B is be under Reverse biased and acts as open switch doesn’t allow to follow current towards Ground and stop conducting. The collector diode goes into Forward biased conduction, forcing Q2 base to go high. This in turn saturates Q4 producing output low.